For the permanent storage of data, nonvolatile EEPROM cells are usually used. Various technologies have been proposed for realising EEPROM cells (see, for example, Lai et al., IEDM Tech. Dig., 1986, pages 580-583).
On the one hand, specific MOS transistors are used as memory cells in the so-called SONOS or MNOS cells. The MOS transistor comprises a gate dielectric comprising at least one silicon oxide layer underneath the gate electrode and a silicon oxide layer between the silicon nitride layer and the channel region. In order to store information, charge carriers are stored in the silicon nitride layer.
The silicon oxide layer has a maximum thickness of 2.2 mm in SONOS cells. The silicon nitride layer usually has a thickness of about 10 nm in modern SONOS memories. A further silicon oxide layer, having a thickness of 3 to 4 nm, is usually provided between the silicon nitride layer and the gate electrode. These nonvolatile memory cells can be written to and erased electrically. During a writing operation, a voltage is applied to the gate electrode such that charge carriers tunnel from the substrate through the silicon oxide layer having a maximum thickness of 2.2 nm into the silicon nitride layer. For erasure, the gate electrode is connected up in such a way that the charge carriers stored in the silicon nitride layer tunnel through the silicon oxide layer having a thickness of 2 nm into the channel region and charge carriers of the opposite conductivity type tunnel from the channel region through the silicon oxide layer into the silicon nitride layer.
SONOS cells having a time period of .ltoreq.10 years for data retention. This time period is too short for many applications, for example for the storage of data in computers.
EEPROM cells with floating gate are used as an alternative to the SONOS cells. These EEPROM cells are suitable for applications in which longer time periods are required for data retention. In these memory cells, a floating gate electrode, which is completely surrounded by dielectric material, is arranged between a control gate electrode and the channel region of the MOS transistor. The information is stored in the form of charge carriers on the floating gate electrode. These memory cells, which are also referred to as FLOTOX cells, can be written to and erased electrically. For this purpose, the control gate electrode is connected to a potential such that charge carriers flow from the channel region onto the floating gate electrode (writing) or charge carriers flow from the floating gate electrode into the channel region (erasure). These FLOTOX cells have time periods of &lt; than 150 years for data retention.
However, they have a complicated structure in comparison with the SONOS cells. Furthermore, FLOTOX cells require more space than SONOS cells since the control gate electrode must laterally overlap the floating gate electrode. Finally, the so-called radiation hardness of FLOTOX cells is limited. Radiation hardness refers to the insensitivity of the stored charge to external radiation sources and/or electromagnetic fields.
In order to increase the storage density in FLOTOX cells, it has been proposed (see, for example, Lai et al., IEDM Tech. Dig., 1986, pages 580-583) to store information in the sense of multi-value logic. In this case, more than 3 logic values are stored by unambiguously assigning a threshold voltage value of the MOS transistor to each logic value. In the course of programming, the different threshold voltage values are set, in dependence on the logic value to be stored, by injecting different quantities of charge.